1. Field of the Invention
The present invention relates to multibit signal communication apparatuses using optical or electric signals, and to clock signal reproduction transmission systems for extracting a clock signal for redigitizing data signals that have been transmitted. In particular, the invention relates to techniques for ensuring reliability in the event an abnormality develops in some of the bits in the data signals by allowing communication to continue using the remaining normal bits.
2. Background Art
Information processing apparatuses such as switching systems and routers employ an optical or electric signal communication apparatus for carrying out data communications. In a receiver portion of such a signal communication apparatus, it is necessary to render a reception data signal into a digital signal synchronized with the internal clock signal of the apparatus so that signal processing can be carried out in the apparatus. For this purpose, in the receiver portion of the signal communication apparatus in general, a step is carried out before synchronizing the data signal with the internal clock signal whereby a clock signal with an adjusted phase relationship with the data signal and the data signal are fed to a flip-flop circuit to reproduce a data signal synchronized with the clock signal. This clock signal is referred to as a reproduction clock signal. The data signal synchronized with the reproduction clock signal can be easily synchronized with the internal clock signal by digital processing such as phase adjustment or demultiplexing.
JP Patent Publication (Kokai) No. 2001-44974 A discloses an apparatus comprising an N-transmission line interface panel that accommodates individual transmission paths for N-lines and that extracts a clock signal from each of reception data signals. The apparatus also comprises a clock signal distribution panel for producing an internal clock signal and a transmission-path interface panel that constitutes a preliminary package. The clock signal distribution panel has an active line state monitoring circuit. The transmission-path interface panel includes a clock signal extraction circuit, an extraction-reference clock signal generation circuit, a clock signal control circuit, and a state-signal selection circuit. The extracted clock signal is phase-adjusted so as to be synchronized with the internal clock signal.
When the communication speed is relatively low, a clock signal parallel transmission system is used whereby the clock signal that has been transmitted simultaneously and in parallel with data signal is used as the reproduction clock signal. However, when the communication speed is more than 1 Gbps, the clock signal parallel transmission system produces large timing variations between the data signal and the clock signal, known as “bit skew”, so that the parallely transmitted clock signal cannot be used as the reproduction clock signal as is. Thus, in high-speed signal communications, a clock signal reproduction transmission system is employed. In this system, instead of transmitting the clock signal in parallel with the data signal, a clock signal is extracted from the data signal by means of a phase-locked oscillator, for example. The clock signal is then used as the reproduction clock signal.
In recent years, a multibit clock signal reproduction transmission system is increasingly used in which the number of signal bits between signal communication apparatuses is increased in order to further increase the transmission speed. An example where such a multibit clock signal reproduction transmission system is applied to an IC for cable transceivers is described in the MAXIM product catalog, Quad 2.5 Gbps Cable Transceiver MAX3780, available from Maxim Integrated Products.
Referring to FIG. 14, the structure of the signal communication apparatus using the clock signal reproduction transmission system according to the prior art will be described. As shown in FIG. 14, numeral 1401 designates a signal communication apparatus A that transmits an n-bit (where n is an integer greater than 1) data signal. Numeral 1402 designates a signal communication apparatus B that receives the n-bit data signal transmitted from the signal communication apparatus A 1401. Numeral 1403 in the signal communication apparatus A 1401 designates an internal circuit that outputs n-bit data signals Tid1, Tid2, Tid3, . . . Tidn. Numerals 14041, 14042, 14043, . . . 1404n designate output buffer circuits. Numerals 14051, 14052, 14053, . . . 1405n designate transmission lines, such as optical fibers or conductor cables, connecting the apparatus A 1401 and the apparatus B 1402.
Data signals Tid1, Tid2, Tid3, . . . Tidn are outputted via output buffer circuits 14041, 14042, 14043, . . . 1404n to the transmission lines 14051, 14052, 14053, . . . 1405n in the form of optical or electric signals, for example. The n-bit data signals transmitted via the transmission lines are received by input buffer circuits 14061, 14062, 14063, . . . 1406n in the signal communication apparatus B 1402. The input buffer circuits then output n-bit data signals Txd1, Txd2, Txd3, . . . Txdn. The signal communication apparatus B 1402 further includes a clock signal reproduction circuit 1407 and phase adjusting circuits 14081, 14082, 14083, . . . 1408n as circuits for reproducing the data signal. The clock signal reproduction circuit 1407 extracts a reference clock signal SCK from the data signal Txd1. In the phase adjusting circuits 14081, 14082, 14083, . . . 1408n, the phase of the individual data signals Txd1, Txd2, Txd3, . . . Txdn is compared with that of the reference clock signal SCK to produce phase-adjusted reproduction clock signals RCK1, RCK2, RCK3, . . . RCKn for the correct reproduction of a data signal.
Using the data signals Txd1, Txd2, Txd3, . . . Txdn and the reproduction clock signals RCK1, RCK2, RCK3, . . . RCKn, the flip-flop circuits 14091, 14092, 14093, . . . 1409n outputs data signals Tod1, Tod2, Tod3, . . . Todn, which are synchronized with the reproduction clock signal. The data signals Tod1, Tod2, Tod3, . . . Todn synchronized with the reproduction clock signals are received by an internal circuit 1410.
Thus, the apparatus shown in FIG. 14 is a signal communication apparatus employing the clock signal reproduction transmission system whereby a clock signal is extracted from the data signal Txd1 and then an n-bit data signal is reproduced using the extracted clock signal as the reference clock signal.
In the above-mentioned JP Patent Publication (Kokai) No. 2001-44974 A, the apparatus comprises an N-transmission line interface panel that accommodates individual transmission paths for N-lines and that extracts a clock signal from each of reception data signals. It also comprises a clock signal distribution panel for producing an internal clock signal and a transmission-path interface panel that constitutes a preliminary package. The clock signal distribution panel has an active line state monitoring circuit, and the transmission-path interface panel includes a clock signal extraction circuit, an extraction-reference clock generation circuit, a clock signal control circuit, and a state-signal selection circuit. The extracted clock signal is phase-adjusted so as to be synchronized with the internal clock signal. This circuit apparatus synchronizes the extracted clock signal with the internal clock and then retains it as a standby clock. It does not use the extracted clock signal for the redigitization of a data signal.
In the conventional signal communication apparatus shown in FIG. 14, in case an abnormality develops in the data signal Txd1 from which the reference clock signal SCK is to be extracted, the reference clock signal SCK cannot be extracted. As a result, it would become impossible to produce the reproduction clock signals based on the reference clock signal in all of the bits. Then, it would become impossible to conduct all-bit signal communications even if the data signals Txd2, Txd3, . . . Txdn for bits other than that of the data signal Txd1 are normal. If a defect were to instantaneously disable signal communication, the participants in the communication would suffer greatly. Communication failure must therefore be responded to immediately by replacing the affected signal communication apparatus, but it is impossible to provide planned restoration work. Thus, it is costly to manage and maintain the signal communication apparatuses.
In order to prevent such a signal communication interruption in times of failure, the signal communication apparatuses could be provided in a dual manner. According to this method, should a failure occur in one of the signal communication apparatuses, the other signal communication apparatus can be operated so that no signal communication interruption occurs during failure. In this method, the number of bits available in the event of failure is 50% of that available during normal operation. However, the cost per bit of data signal increases with increasing transmission speed, and so the dual provision of signal communication apparatuses is disadvantageous in terms of cost.
In another method for preventing the interruption of signal communication in the event of failure, each bit of the data signals could be provided with a clock signal reproduction circuit so that the clock signal can be extracted for each bit. In this method, if failure occurs in one bit of a data signal, clock signals can be obtained from the other bits and the reproduction clock signals can be produced. The available bits during failure in this method are (n−1)/n×100% of the bits available during normal operation, where n is the number of bits in the data signal and is an integer greater than 1. In recent years, however, it is becoming increasingly common to mount a multibit data signal communication reception circuit on a single LSI chip. Thus, when the data signal has n bits, a number n of clock signal reproduction circuits must be provided for the single LSI chip. As the clock signal reproduction circuit has a larger area than that of other reception circuits such as signal input circuits, the required area of the LSI becomes greater and the cost increases. In general, the clock signal reproduction circuit employs a phase synchronizing circuit that tends to become the source of noise, which destabilizes the operation. Accordingly, mounting many clock signal reproduction circuits on a single LSI chip creates the problem of noise between clock signal reproduction circuits, which is difficult to solve in terms of LSI development.
Particularly in signal communication apparatuses that employ light, where an oscillator for producing light is provided for each bit, failure whereby one bit of data signal develops an abnormality occurs relatively often, and it is very important to provide countermeasures.